1. Technical Field
The present disclosure relates to an image sensor, and more particularly, to a stack chip package image sensor in which a capacitor for noise reduction is formed in a bottom wafer in correspondence with a unit pixel of a top wafer, so that it is possible to improve noise characteristics of the image sensor.
2. Related Art
In general, a CMOS image sensor (CIS) may be classified into a FSI (Front Side Illumination) image sensor and a BSI (Back Side Illumination) image sensor.
In a conventional FSI CMOS image sensor, it is not possible to arrange a capacitor for noise reduction in each unit pixel due to a structural problem. Recently, high pixel and pixel miniaturization have been demanded for the FSI CMOS image sensor. However, such a CMOS image sensor has an insufficient space where a capacitor for noise reduction may be arranged in each unit pixel.
In spite of the problem, when a capacitor for noise reduction is arranged in the FSI CMOS image sensor, a capacitor C for noise reduction may be arranged on an incident path of a photodiode PD in a MIM (Metal Insulator Metal) or MOM (Metal on Metal) structure as illustrated in FIG. 1.
In such a case, there is a problem that a light incident area of the photodiode PD is reduced inversely proportional to an installation area of the capacitor for noise reduction. Therefore, in the FSI CMOS image sensor, it is not possible to arrange the capacitor for noise reduction.
However, in the case of a conventional BSI CMOS image sensor, a capacitor for noise reduction may be formed in a rear direction of a photodiode PD by using a metal layer with a MIM or MOM structure on the basis of incident light. Consequently, the capacitor for noise reduction is formed, so that it is possible to prevent an area of the photodiode PD from being reduced.
However, in such a case, there is a problem that the incident light may be reflected from the surface of the metal layer and thus crosstalk may occur. Furthermore, since the capacitor for noise reduction is formed in the MIM or MOM structure in order to maximally reduce the size of an image sensor chip, it is difficult to design the capacity or the capacitor for noise reduction at a desired value.